Solder bumps for flip chip assembly are deposited be electroplating on the I/O pads of the chips. The basic process steps of wafer bumping are sputtering of a seed layer (UBM), photolithography, electroplating of bump metal, etching of seed layer and reflow. Bump structures of Au, Cu, Ni, SnAg, SnCu, SnAu with a dimension of min. 20 µm and with a pitch of 40 µm and height variation of less than <2 µm (8“) for bumps (25 µm height can be realized by electroplating.
Fan-In & Fan-Out Wafer Level Packaging enables ultra-thin, high-performance semiconductor packages by embedding dies directly on reconstructed wafers with advanced redistribution layer (RDL) technology.
Fan-In WLP: Compact, low-pin-count applications (e.g., mobile, IoT).
Fan-Out WLP: Higher I/O density, multi-die integration, and design flexibility.
Thinner profiles, better electrical performance, scalability, cost efficiency, and high reliability — making FIWLP and FOWLP ideal for next-generation electronics.
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Panel level packaging (PLP) offers a promising approach to semiconductor manufacturing with a focus on larger panels, such as 510x600 mm. This process involves assembling and packaging multiple die in parallel on large substrates, utilizing advanced lamination technology for enhanced structural integrity and thermal performance. Lamination helps ensure uniform thickness and improved bonding strength across the entire panel, making it highly suitable for high-volume production.
Key benefits of PLP include increased throughput, reduced cost per unit, and the ability to integrate more functional components into a single panel. The use of lamination technology further optimizes the manufacturing process, resulting in more reliable products with superior performance.
Advanced Technology Meister Programme (ATMP) is a customised upskilling / reskilling certification programme for high skilled talent development; lead by the industry, and endorsed by the academia to meet industry needs.
